This is probably the most unsuitable place to post such a question, but it's the only question in my assignment that I can't answer (and therefore can't submit and get mullered this weekend)
You are given a 2-level paging system that uses virtual memory architecture with 48 bit virtual addresses. The system has 128, 000 gigabytes of physical memory and 32K byte page size.
a. Illustrate, using a diagram, how address translation (virtual address to physical address) is accomplished for the above system. To get a full mark, you must show how the various fields of each address are interpreted and the size of each field (in bits) on the diagram.
Any ideas?